Pseudo dual port memory with dual latch flip-flop
US9324416B2 · kind B2 · utility
3Cited by
9References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Aug 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.