Method of creating a maskless air gap in back end interconnections with double self-aligned vias
US9324652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2015 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Feb 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.