Method and system for height registration during chip bonding
US9324682B2 · kind B2 · utility
3Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Apr 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S5/0237
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of fabricating a composite semiconductor structure is provided. Pedestals are formed in a recess of a first substrate. A second substrate is then placed within the recess in contact with the pedestals. The pedestals have a predetermined height so that a device layer within the second substrate aligns with a waveguide of the first substrate, where the waveguide extends from an inner wall of the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.