Memory devices having semiconductor patterns on a substrate and methods of manufacturing the same
US9324727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Feb 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device may include a plurality of semiconductor patterns on a substrate including a plurality of first impurity regions doped at a first impurity concentration, a plurality of second impurity regions at portions of the substrate contacting the plurality of semiconductor patterns and doped at a second impurity concentration, a plurality of channel patterns on the plurality of semiconductor patterns, a plurality of gate structures, a plurality of third impurity regions at portions of the substrate adjacent to end portions of the plurality of gate structures, and a plurality of fourth impurity regions at portions of the substrate between the second and third impurity regions and between adjacent second impurity regions. The plurality of fourth impurity regions may be doped at a third impurity concentration which may be lower than the first and second impurity concentrations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.