Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature
US9325324B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2014 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Dec 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) circuit includes a phase comparison circuit configured to compare phase of an input signal to phase of a feedback signal and generate a control signal responsive to the phase comparison and an oscillator circuit configured to generate an output signal at a frequency set by said control signal, where said feedback signal is derived from said output signal. The PLL circuit further operates in a calibration mode of operation wherein the oscillator circuit operates in a frequency locked loop mode to compare frequency of the input signal to frequency of the output signal and center a gain of the oscillator circuit across process, voltage and temperature in response to the frequency comparison. Furthermore, bias current for a charge pump within the phase comparison circuit is calibrated during calibration mode of operation to match a temperature independent reference current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.