Power-scalable skew compensation in source-synchronous parallel interfaces
US9325542B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2012 |
| Grant date | Apr 26, 2016 |
| Priority date | — |
| Expiry date | Mar 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0025
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A parallel receiver interface includes a plurality of parallel data receivers, each receiver receiving input data. A clock receiver is configured to receive a forwarded clock. A phase interpolator has an input coupled to the output of the clock receiver and has an output coupled to each of the parallel receivers. Parallel clock delay elements are within each of the parallel data receivers, each clock delay element configured to provide varying amounts of clock phase adjustment. Inputs of a multiplexer circuit within each of the parallel data receivers are coupled to the outputs of each of the parallel clock delay elements within a respective parallel data receiver. An output of the multiplexer circuit is coupled to a data sampler within the respective parallel data receiver, the multiplexer circuit being configured to be controlled by a logic signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.