High-level language code sequence optimization for implementing programmable chip designs
US9329847B1 · kind B1 · utility
0Cited by
60References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2013 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Mar 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the processes. Having separate read and write processes allows an arbitrary number of sequential reads/writes to occur in any order, subject to buffer size, allowing bursting/sequential transactions that are more efficient than random accesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.