Patent · US Active

Suppressing virtual address translation utilizing bits and instruction tagging

US9330017B2 · kind B2 · utility

17Cited by

8References

10Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Joerg Deutschle · Winnenden, DE
Ute Gaertner · Schenefeld, DE
Lisa C. Heller · Rhinebeck, US

Key dates

Filing date	Nov 2, 2012
Grant date	May 3, 2016
Priority date	—
Expiry date	Apr 30, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/682
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) translates a first virtual address for a first instruction into a first physical address. The TCUEP detects a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB and purging of certain entries in the TLB. The TCUEP translates a second virtual address for a second instruction into a second physical address and stores the second physical address in a second entry in the TLB. The TCUEP configures a second marker in the second entry to indicate that the hit suppression is not allowed for the second entry, and that the purging is not allowed for the second entry. The TCUEP receives a first address translation request that indicates a hit in the second entry. The TCUEP resolves the first address translation request by returning the second physical address.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.