Inventor · Rhinebeck, NY, US

Lisa C. Heller

185Patents
20h-index
81Co-inventors
93Inventor score

Filing activity: Oct 23, 1990 → Aug 4, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US5317754A Method and apparatus for enabling an interpretive execution subset Physics 99 Expired
US5465374A Processor for processing data string by byte-by-byte Physics 94 Expired
US7197601B2 Method, system and program product for invalidating a range of selected storage translation table entries Physics 59 Expired
US7284100B2 Invalidating storage, clearing buffer entries, and an instruction therefor Physics 57 Expired
US6996698B2 Blocking processing restrictions based on addresses Physics 34 Expired
US8086811B2 Optimizations of a perform frame management function issued by pageable guests Physics 33 Active
US5608887A Method of processing data strings Physics 30 Expired
US5619715A Hardware implementation of string instructions Physics 29 Expired
US8103851B2 Dynamic address translation with translation table entry format control for indentifying format of the translation table entry Physics 28 Active
US8176279B2 Managing use of storage by multiple pageable guests of a computing environment Physics 25 Active
US8364912B2 Use of test protection instruction in computing environments that support pageable guests Physics 23 Active
US8380907B2 Method, system and computer program product for providing filtering of GUEST2 quiesce requests Physics 23 Active
US9330018B2 Suppressing virtual address translation utilizing bits and instruction tagging Physics 22 Active
US8909899B2 Emulating execution of a perform frame management instruction Physics 22 Active
US8041923B2 Load page table entry address instruction execution based on an address translation format control field Physics 22 Active
US8452942B2 Invalidating a range of two or more translation table entries and instruction therefore Physics 22 Active
US9092382B2 Reducing microprocessor performance loss due to translation table coherency in a multi-processor system Physics 22 Active
US8117417B2 Dynamic address translation with change record override Physics 21 Active
US8387049B2 Facilitating processing within computing environments supporting pageable guests Physics 20 Active
US8032716B2 System, method and computer program product for providing a new quiesce state Physics 20 Active
US8417916B2 Perform frame management function instruction for setting storage keys and clearing blocks of main storage Physics 19 Active
US9330017B2 Suppressing virtual address translation utilizing bits and instruction tagging Physics 17 Active
US9697135B2 Suppressing virtual address translation utilizing bits and instruction tagging Physics 17 Active
US9069715B2 Reducing microprocessor performance loss due to translation table coherency in a multi-processor system Physics 17 Active
US7827321B2 Central processing unit measurement facility Physics 16 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.