Patent · US Active

Suppressing virtual address translation utilizing bits and instruction tagging

US9330018B2 · kind B2 · utility

22Cited by

8References

5Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Joerg Deutschle · Winnenden, DE
Ute Gaertner · Schenefeld, DE
Lisa C. Heller · Rhinebeck, US

Key dates

Filing date	Feb 26, 2013
Grant date	May 3, 2016
Priority date	—
Expiry date	May 3, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/682
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Some embodiments include a method that can store a first physical address in a first entry in a translation lookaside buffer (TLB). The method can configure a first marker in the first entry in the TLB to indicate that hit suppression is allowed for the first entry. The method can detect a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB, and cause purging of certain entries in the TLB. The method can translate a second virtual address for a second instruction into a second physical address. The method can store the second physical address in a second entry. The method can configure a second marker in the second entry in the TLB to indicate that the hit suppression is not allowed for the second entry in the TLB, and that the purging is not allowed for the second entry in the TLB.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.