Processing device and method thereof
US9330024B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2014 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Dec 5, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/65
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device comprises inter alia a monolithic memory accumulator unit, which exposes a virtual memory space to an interconnect bus and comprises a conversion table with translation information to translate requests with virtual addresses into requests with physical addresses. The MMA is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to pass on transaction request(s) to storage locations of an integrated peripheral.A processing device comprises at least one integrated peripheral, IP, with an accessibility adapter unit, AA, which exposes a virtual memory space to the interconnect bus 650 and which comprises a conversion table with translation information. The AA 150 is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to route transaction request(s) to storage locations of the IP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.