Read operation based aging sensor for static random access memory (SRAM)
US9330785B1 · kind B1 · utility
1Cited by
4References
30Claims
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Key dates
| Filing date | Apr 29, 2015 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Apr 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a static random access memory (SRAM), such as an SRAM cache in a processor or system-on-a-chip (SoC) device, an aging sensor is provided for testing degradation of SRAM cells comprising p-channel metal oxide semiconductor (PMOS) transistors. The minimum power supply voltage VDDMIN for the SRAM may be dynamically scaled up as the SRAM ages by performing read tests with and without the wordline overdrive voltage VWLOD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.