Patent · US Active

SOC design with critical technology pitch alignment

US9331016B2 · kind B2 · utility

9Cited by

8References

15Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Xiangdong Chen · Irvine, US
Ohsang Kwon · San Diego, US
Esin Terzioglu · San Diego, US
Hadi Bunnalim · San Diego, US

Key dates

Filing date	Jul 22, 2014
Grant date	May 3, 2016
Priority date	—
Expiry date	Jul 22, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g2+m2≧v2 and an LCM of g and m is less than 20 g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2>m and the LCM of g, m, and m2 is less than 20 g.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.