Chip package incorporating interfacial adhesion through conductor sputtering
US9331017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2014 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Oct 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.