Bonded stacked wafers and methods of electroplating bonded stacked wafers
US9331048B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2015 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Jan 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30101
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method including: providing a first wafer stack; applying a first bonding layer on the first wafer stack; providing a second wafer stack, where the second wafer stack includes vias; and applying a second bonding layer to the second wafer stack. The vias extend through the second wafer stack and to the second bonding layer. The second bonding layer is bonded to the first bonding layer. A seed layer is applied on a side of the second wafer stack opposite the second bonding layer such that a material of the seed layer (i) contacts the vias, and (ii) extends over and past ends of the second wafer stack and onto the first bonding layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.