Semiconductor package assembly with decoupling capacitor
US9331054B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2014 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Feb 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/1053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. A second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. A dynamic random access memory (DRAM) device is mounted on the second device-attach surface. A decoupling capacitor is mounted on the second device-attach surface. Conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.