Patent · US Active

Chip, chip package and die

US9331059B2 · kind B2 · utility

0Cited by

3References

23Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Robert Allinger · Unterhaching, DE
Gottfried Beer · Nittendorf, DE
Juergen Hoegerl · Regensburg, DE

Key dates

Filing date	Dec 10, 2013
Grant date	May 3, 2016
Priority date	—
Expiry date	Dec 10, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/60
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.