Parallel connection methods for high performance transistors
US9331061B2 · kind B2 · utility
8Cited by
34References
46Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2012 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Nov 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/82
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Parallel transistor circuits with reduced effects from common source induction. The parallel transistors include physical gate connections that are located electrically close to one another. The parallel circuits are arranged such that the voltage at the common gate connection resulting from transient currents across common source inductance is substantially balanced. The circuits include switching circuits, converters, and RF amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.