Semiconductor-on-insulator integrated circuit with reduced off-state capacitance
US9331098B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2014 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | Sep 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit assembly comprises an insulating layer, a semiconductor layer, a handle layer, a metal interconnect layer, and transistors. The insulating layer has a first surface, a second surface, and a hole extending from the first surface to the second surface. The semiconductor layer has a first surface and a second surface, the first surface of the semiconductor layer contacting the first surface of the insulating layer. The handle layer is coupled to the second surface of the semiconductor layer. The metal interconnect layer is coupled to the second surface of the insulating layer, the metal interconnect layer being disposed within the hole in the insulating layer. The transistors are located in the semiconductor layer. The hole in the insulating layer extends to at least the first surface of the semiconductor layer. The metal interconnect layer electrically couples a plurality of the transistors to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.