Semiconductor devices having hybrid capacitors and methods for fabricating the same
US9331140B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2015 |
| Grant date | May 3, 2016 |
| Priority date | — |
| Expiry date | May 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.