Method for making HKMG dummy gate structure with amorphous/ONO masking structure and procedure

US9331172B2 · kind B2 · utility

Assignee

• INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Chunlong Li · Beijing, CN
• Junfeng Li · Nanhu, CN
• Jiang Yan · Beijing, CN
• Lingkuan Meng · Beijing, CN
• Xiaobin He · Los Angeles, US
• Guanglu Chen · Beijing, CN
• Chao Zhao · Thuwal, SA

Key dates

• Filing date: Nov 13, 2012
• Grant date: May 3, 2016
• Expiry date: Nov 13, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32139
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.