Jiang Yan
50Patents
8h-index
65Co-inventors
81Inventor score
Filing activity: May 4, 1994 → May 18, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7298009B2 | Semiconductor method and device with mixed orientation substrate | Electricity | 544 | Expired |
| US8173502B2 | Formation of active area using semiconductor growth process without STI integration | Electricity | 123 | Active |
| US5578848A | Ultra thin dielectric for electronic devices and method of making same | Emerging Cross-Sectional Technologies | 83 | Expired |
| US5478765A | Method of making an ultra thin dielectric for electronic devices | Emerging Cross-Sectional Technologies | 28 | Expired |
| US6864151B2 | Method of forming shallow trench isolation using deep trench isolation | Electricity | 23 | Expired |
| US7651915B2 | Strained semiconductor device and method of making same | Electricity | 13 | Active |
| US7495279B2 | Embedded flash memory devices on SOI substrates and methods of manufacture thereof | Electricity | 11 | Active |
| US7482215B2 | Self-aligned dual segment liner and method of manufacturing the same | Electricity | 9 | Active |
| US8158478B2 | Strained semiconductor device and method of making same | Electricity | 6 | Active |
| US8501500B2 | Method for monitoring the removal of polysilicon pseudo gates | Electricity | 5 | Active |
| US9070744B2 | Shallow trench isolation structure, manufacturing method thereof and a device based on the structure | Electricity | 5 | Active |
| US8759208B2 | Method for manufacturing contact holes in CMOS device using gate-last process | Electricity | 5 | Active |
| US8502299B2 | Strained semiconductor device and method of making same | Electricity | 5 | Active |
| US8530355B2 | Mixed orientation semiconductor device and method | Electricity | 5 | Active |
| US7517767B2 | Forming conductive stud for semiconductive devices | Electricity | 5 | Active |
| US7393746B2 | Post-silicide spacer removal | Electricity | 4 | Active |
| US7186622B2 | Formation of active area using semiconductor growth process without STI integration | Electricity | 4 | Expired |
| US8031532B2 | Methods of operating embedded flash memory devices | Electricity | 3 | Active |
| US7800182B2 | Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same | Electricity | 3 | Active |
| US7687347B2 | Embedded flash memory devices on SOI substrates and methods of manufacture thereof | Electricity | 3 | Active |
| US8319285B2 | Silicon-on-insulator chip having multiple crystal orientations | Electricity | 3 | Expired |
| US8853024B2 | Method of manufacturing semiconductor device | Electricity | 2 | Active |
| US8541296B2 | Method of manufacturing dummy gates in gate last process | Electricity | 2 | Active |
| US7985642B2 | Formation of active area using semiconductor growth process without STI integration | Electricity | 1 | Active |
| US7786547B2 | Formation of active area using semiconductor growth process without STI integration | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.