Integrated device test circuits and methods
US9335375B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2011 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Feb 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/50
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Test circuits and methods for detecting faults in integrated devices are disclosed. In an embodiment, a circuit may include an input node configured to receive a test signal, and a transition circuit configured to generate a transit on at least one voltage level indicator pin dependent on the test signal. The circuit may also include a data capture circuit configured to capture the output of the at least one voltage level indicator pin to test for stuck-at faults. In another embodiment, a method may include receiving a test signal, generating a transit on at least one voltage level indicator pin dependent on the test signal, and capturing the output of the at least one voltage level indicator pin to test for stuck-at faults.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.