Memory device for reducing a write fail, a system including the same, and a method thereof
US9335951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2013 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Jan 28, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.