Dynamic design partitioning for diagnosis
US9336107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2012 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Apr 19, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/26
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.