Capacitor array and layout design method thereof
US9336347B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2013 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Jan 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/442
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout design method is provided for generating capacitor arrays being described in four steps: first, the wiring mode of unit capacitors is defined allowing the wire being connected to the upper plate to parallel that to the lower one, second, a capacitor array layout is designed with capacitors being distributed in Mh lines, Mh is the maximum of capacitors' lines, the line numbers of Class 1 to Class K capacitors are defined in the unilateral capacitor array, third, the wiring mode is set for capacitor array making sure the lengths of the wires to the upper and lower plates of unit capacitors are equal, at last, parasitic parameters are characterized in ways that verify the layout. A capacitor array is provided as well. By eliminating capacitance mismatching caused by parasitic capacitance, the method works to generate a well-matched capacitor array in an easy and efficient way.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.