Patent · US Active

Method for removing hard mask oxide and making gate structure of semiconductor devices

US9337103B2 · kind B2 · utility

2Cited by
9References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 7, 2012
Grant dateMay 10, 2016
Priority date
Expiry dateDec 7, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/0135

Abstract

A method includes forming a first gate above a semiconductor substrate, forming a hard mask on the first gate, and forming a contact etch stop layer (CESL) on the hard mask. No hard mask is removed between the step of forming the hard mask and the step of forming the CESL. The method further includes forming an interlayer dielectric (ILD) layer over the CESL, and performing one or more CMP processes to planarize the ILD layer, remove the CESL on the hard mask, and remove at least one portion of the hard mask.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.