Hermetic wafer level packaging
US9337168B2 · kind B2 · utility
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2References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Feb 6, 2014 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Feb 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.