Metal gate stack having TaAlCN layer
US9337192B2 · kind B2 · utility
11Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2014 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Nov 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a semiconductor substrate; and a gate stack disposed over the semiconductor substrate. The gate stack further includes a gate dielectric layer disposed over the semiconductor substrate; a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer comprises tantalum aluminum carbon nitride (TaAlCN); a work function layer disposed over the multi-function blocking/wetting layer; and a conductive layer disposed over the work function layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.