High voltage power semiconductor device on SiC
US9337277B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2014 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Sep 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
4H SIC epiwafers with thickness of 50-100 μm are grown on 4° off-axis substrates. Surface morphological defect density in the range of 2-6 cm−2 is obtained from inspection of the epiwafers. Consistent carrier lifetime in the range of 2-3 μs has been obtained on these epiwafers. Very low BPD density has been confirmed in the epiwafers with BPD density down to below 10 cm−2. Epitaxial wafers with thickness of 50-100 μm have been used to fabricate diodes. High voltage testing has demonstrated blocking voltages near the theoretical values for 4H-SiC. Blocking voltage as high as 8 kV has been achieved in devices fabricated on 50 μm thick epitaxial films, and blocking voltage as high as 10 kV has been obtained in devices fabricated on 80 μm thick films. Failure analysis confirmed triangle defects, which form from surface damage or particles present during epitaxy, are killer defects and cause the device to fail in reverse bias operation. In addition, the leakage current at the high blocking voltages of the JBS diodes showed no correlation with the screw dislocation density. It is also observed that the main source of basal plane dislocations in the epilayer originates in the crystal grow…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.