Buffer circuit for voltage controlled oscillator
US9337818B1 · kind B1 · utility
2Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2015 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Aug 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer circuit includes an inverter and a level-shifter. The inverter receives a first oscillating signal at a first voltage level and generates an inverted version of the first oscillating signal at a second voltage level. The level-shifter receives a second oscillating signal at a third voltage level, which has a phase difference from the first oscillating signal, and the inverted first oscillating signal, and generates a buffer output signal at a fourth voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.