Cache memory system and method using dynamically allocated dirty mask space
US9342461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2012 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Jul 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/604
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory system includes a cache memory including a plurality of cache memory lines and a dirty buffer including a plurality of dirty masks. A cache controller is configured to allocate one of the dirty masks to each of the cache memory lines when a write to the respective cache memory line is not a full write to that cache memory line. Each of the dirty masks indicates dirty states of data units in one of the cache memory lines. The cache controller may include a dirty buffer index which stores an identification (ID) information that associates the dirty masks with the cache memory lines to which the dirty masks are allocated. A cache line may include a fully dirty flag indicating when each byte in that cache line is dirty, so that a dirty mask does not need to be allocated for that cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.