Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions
US9342639B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2015 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Feb 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Timing analysis of a chip component using feedback assertions without disrupting the timing of internal latch to latch paths in the chip component maintaining timing accuracy for all the boundary paths. This is achieved by using slack based feedback assertions for non-clock chip inputs and outputs which are used to dynamically derive the arrival time or the required arrival time assertions. The assertions on the clock inputs are not updated via feedback assertions to facilitate non-disruption of the latch to latch path timing. The timing non-disruption of the resulting latch to latch paths of the chip component increases the designer productivity during timing closure resulting in a shortened time to take the chip design through timing closure to manufacturing. This method is applicable for statistical as well as deterministic timing analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.