Patent · US Active

Frequency selection granularity for integrated circuits

US9343126B2 · kind B2 · utility

2Cited by

14References

15Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Harikrishna B. Baliga · Folsom, US
Peter J. Smith · Folsom, US
Joydeep Ray · Folsom, US

Key dates

Filing date	Dec 28, 2012
Grant date	May 17, 2016
Priority date	—
Expiry date	Apr 14, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/18
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Clock signal generation circuitry. A frequency multiplier is coupled to receive a clock signal and to generate a frequency-multiplied clock signal. A switching circuit is coupled to receive at least two reference clock signals. The switching circuit provides one of the reference clock signals in response to a reference select signal. A phase locked loop (PLL) is coupled to receive the frequency-multiplied clock signal and the selected reference clock signal. The PLL generates an output clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.