Non-volatile semiconductor storage device
US9343166B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2013 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Jun 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory includes a plurality of word lines, power supply units are provided for word line columns, a different unit voltage is applied for each of power supply units depending on whether a selected memory cell exists in the column, a switching mechanism in each power supply unit is switched by the word line depending on a voltage value on a control line, a charge storage gate voltage or inhibition gate voltage is applied for each of the word lines so that the inhibition gate voltage value and a bit line voltage value can be freely set for each of the word line columns to values at which occurrence of disturbance can be suppressed. A plurality of power supply units are connected to the control line in a common row direction, and a row-direction address decoder, which is independent for each of the word line columns is not required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.