Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices
US9343303B2 · kind B2 · utility
8Cited by
16References
19Claims
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Key dates
| Filing date | Sep 12, 2014 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Oct 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/67
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming strain-relaxing semiconductor layers are provided in which a porous region is formed in a surface of a semiconductor substrate. A first semiconductor layer that is lattice-matched with the semiconductor substrate is formed on the porous region. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer being a strained layer as formed. The second semiconductor layer is then relaxed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.