Integrated circuit using deep trench through silicon (DTS)
US9343352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2015 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Jan 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.