Three-dimensional memory device with stress compensation layer within a word line stack
US9343358B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2015 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Feb 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first stack of alternating layers including first insulating layers and first sacrificial material layers is formed on a substrate. Dielectric oxide layers applying compressive stress are formed on the top surface of the first stack and on the bottom surface of the substrate. A second stack of alternating layers including second insulating layers and second sacrificial material layers is formed over the top dielectric oxide layer. After formation of lateral recesses by removal of the first and second sacrificial material layers, a bottom dielectric oxide layer is removed. A conductive material applying a tensile stress is deposited into the backside recesses to form electrically conductive layers. The compressive stress applied by the top dielectric oxide layer partially cancels the tensile stress applied by the electrically conductive layers, and reduces the curvature of the substrate that has a concave bottom surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.