Imagers with stacked integrated circuit dies
US9343497B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 13, 2013 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Apr 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An imager may include an imaging die that is stacked with an image processing die. The imaging die may generate output signals from received light. The image processing die may process the output signals. Through-silicon vias of the imaging die or solder balls may electrically couple the imaging die to the image processing die and convey the output signals to the image processing die. The imaging die may include a pixel array that generates pixel signals from the received light. The image processing die may generate control signals that control the imaging die and are conveyed to the imaging die over the through-silicon vias or solder balls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.