Nanowire transistor devices and forming techniques

US9343559B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Glenn A. Glass · Portland, US
• Kelin J. Kuhn · Beaverton, US
• Seiyon Kim · Portland, US
• Anand S. Murthy · Beaverton, US
• Daniel B. Aubertine · North Plains, US

Key dates

• Filing date: Apr 20, 2015
• Grant date: May 17, 2016
• Expiry date: Apr 20, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.