Inventor · North Plains, OR, US

Daniel B. Aubertine

8Patents
4h-index
18Co-inventors
50Inventor score

Filing activity: Jul 27, 2012 → Oct 6, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US9728464B2 Self-aligned 3-D epitaxial structures for MOS device fabrication Electricity 25 Active
US9343559B2 Nanowire transistor devices and forming techniques Electricity 22 Active
US9812524B2 Nanowire transistor devices and forming techniques Electricity 9 Active
US10373977B2 Transistor fin formation via cladding on sacrificial core Electricity 4 Active
US9893149B2 High mobility strained channels for fin-based transistors Electricity 2 Active
US10403626B2 Fin sculpting and cladding during replacement gate process for transistor channel applications Electricity 0 Active
US12046517B2 Self-aligned 3-D epitaxial structures for MOS device fabrication Electricity 0 Active
US10879241B2 Techniques for controlling transistor sub-fin leakage Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.