Successive approximation analog-to-digital converter and conversion method thereof
US9344105B2 · kind B2 · utility
1Cited by
1References
14Claims
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Key dates
| Filing date | May 5, 2014 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | May 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/687
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.