Negative biased substrate for pixels in stacked image sensors
US9344658B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2014 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Nov 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/811
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel cell includes a photodiode disposed within a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. A transfer transistor is disposed within the first semiconductor chip and coupled to the photodiode to transfer the image charge from the photodiode. A bias voltage generation circuit disposed within a second semiconductor chip for generating a bias voltage. The bias voltage generation circuit is coupled to the first semiconductor chip to bias the photodiode with the bias voltage. The bias voltage is negative with respect to a ground voltage of the second semiconductor chip. A floating diffusion is disposed within the second semiconductor chip. The transfer transistor is coupled to transfer the image charge from the photodiode on the first semiconductor chip to the floating diffusion on the second semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.