Code optimization to enable and disable coalescing of memory transactions
US9348523B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2013 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Sep 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A transactional memory system controls the coalescing of outermost memory transactions. The coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. A processor of the transactional memory system executes a run-time instrumentation program for monitoring and modifying an associated program having a plurality of transactions. The processor initiates execution of the associated program. Based on execution of transactions, by the processor, of the associated program, the run-time instrumentation program dynamically obtains instrumentation information associated with the execution. Based on the obtained instrumentation information, the processor dynamically modifies continued execution of transactions of the associated program to optimize transactional execution (TX).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.