Multi-level tracking of in-use state of cache lines
US9348591B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2011 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Feb 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure includes tracking of in-use states of cache lines to improve throughput of pipelines and thus increase performance of processors. Access data for a number of sets of instructions stored in an instruction cache may be tracked using an in-use array in a first array until the data for one or more of those sets reach a threshold condition. A second array may then be used as the in-use array to track the sets of instructions after a micro-operation is inserted into the pipeline. When the micro-operation retires from the pipeline, the first array may be cleared. The process may repeat after the second array reaches the threshold condition. During the tracking, an in-use state for an instruction line may be detected by inspecting a corresponding bit in each of the arrays. Additional arrays may also be used to track the in-use state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.