Inter-set wear-leveling for caches with limited write endurance
US9348743B2 · kind B2 · utility
0Cited by
8References
20Claims
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Key dates
| Filing date | Feb 21, 2013 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Sep 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache controller includes a first register that updates after every memory location swap operation on a number of cache sets in a cache memory and resets every N−1 memory location swap operations. N is a number of the cache sets in the cache memory. The memory controller also has a second register that updates after every N−1 memory location swap operations, and resets every (N2−N) memory location swap operations. The first and second registers track a relationship between logical locations and physical locations of the cache sets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.