Supporting calibration for sub-rate operation in clocked memory systems
US9349422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2015 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Apr 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., ½, ¼ or ⅛ of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.