Memory devices and memory operational methods including single erase operation of conductive bridge memory cells
US9349450B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2013 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Jan 6, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.