Method for fabricating quasi-SOI source/drain field effect transistor device
US9349588B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2014 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Mar 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method for fabricating a quasi-SOI source/drain field effect transistor device, which comprises the steps of forming an active region of the device; forming a gate stack structure of the device; doping a source/drain extension region, and forming a first layer of side wall at two sides of the gate stack structure; forming a recessed source/drain structure; forming a quasi-SOI source/drain isolation layer; in-situ doping an epitaxial second semiconductor material source/drain, and activating by annealing; removing the previous dummy gate and re-depositing a high-k metal gate, if a post-gate process is employed; and forming contacts and metal interconnections. The method of the invention is well compatible with the existing CMOS process, and it has the features of simple process and small heat budget; and in comparison with the traditional field effect transistor, by means of the quasi-SOI source/drain field effect transistor device fabricated according to the method of the invention, the leakage current can be lowered effectively, thus the power consumption of the device can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.