Inventor · Hubei, CN

Yuancheng Yang

32Patents
1h-index
23Co-inventors
53Inventor score

Filing activity: Mar 28, 2014 → May 20, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US11935596B2 Three-dimensional memory devices having polysilicon layer and bonded semiconductor structures and methods for forming the same Electricity 2 Active
US9502310B1 Integration method for a vertical nanowire transistor Electricity 1 Active
US12020750B2 Three-dimensional memory devices Electricity 1 Active
US12075621B2 Three-dimensional memory device and method for forming the same Electricity 1 Active
US12278209B2 Peripheral circuit having recess gate transistors and method for forming the same Electricity 0 Active
US12327592B2 Vertical memory devices and methods for operating the same Electricity 0 Active
US9349588B2 Method for fabricating quasi-SOI source/drain field effect transistor device Electricity 0 Active
US12027207B2 Vertical memory devices and methods for operating the same Electricity 0 Active
US12300648B2 Three-dimensional memory devices and methods for forming the same Electricity 0 Active
US12388037B2 Three-dimensional memory devices and methods for forming the same Electricity 0 Active
US12262533B2 Dynamic flash memory (DFM) with multi-cells Electricity 0 Active
US12272645B2 Three-dimensional memory devices and fabricating methods thereof Electricity 0 Active
US12082407B2 Three-dimensional memory device and method for forming the same Electricity 0 Active
US12170257B2 Three-dimensional memory devices and methods for forming the same Electricity 0 Active
US12328867B2 Memory devices having vertical transistors and methods for forming the same Electricity 0 Active
US12274055B2 Control gate structures in three-dimensional memory devices and methods for forming the same Electricity 0 Active
US12176309B2 Three-dimensional memory devices and methods for forming the same Electricity 0 Active
US12127393B2 Memory devices having vertical transistors and methods for forming the same Electricity 0 Active
US9425060B2 Method for fabricating multiple layers of ultra narrow silicon wires Electricity 0 Active
US11929119B2 Three-dimensional memory devices and memory system Electricity 0 Revoked
US12082408B2 Three-dimensional memory devices having first semiconductor structure bonded with second semiconductor structure each including peripheral circuit and methods for forming the same Electricity 0 Active
US11996152B2 Three-dimensional memory devices and methods for forming the same Electricity 0 Active
US12388036B2 Three-dimensional memory devices and methods for forming the same Electricity 0 Active
US12322596B2 Methods for thermal treatment of a semiconductor layer in semiconductor device Electricity 0 Active
US12412628B2 Methods for forming three-dimensional memory devices Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.